Digital Electronics Question Paper
Digital Electronics
Course:Bachelor Of Science In Information Technology
Institution: Kca University question papers
Exam Year:2011
UNIVERSITY EXAMINATIONS: 2010/2011
THIRD YEAR EXAMINATION FOR THE DEGREE OF BACHELOR OF
SCIENCE IN INFORMATION TECHNOLOGY
BIT 1202: DIGITAL ELECTRONICS
DATE: APRIL 2011 TIME: 2 HOURS
INSTRUCTIONS: Answer question ONE and any other TWO questions
QUESTION ONE
a) Perform the following conversions;
i) 693.56 (decimal) to Octal, corrected to 4 fractional places of Octal.
ii) 437.6 (octal) to Hexadecimal (6 Marks )
b) Copy and fill the Multiplication table for the Octal (base-8) given by the formula,
P(8) = A(8) x B (8) show your working how you have obtained P1 to P8. (4 Marks)
X A 4 7 5
B
6
3
2
Px
X
X
X
X
P1
14
P6
X
P2
P4
P7
X
P3
P5
P8
Example: For A = 4 and B = 3, Px = 14.
c) Given that only NOR-gates are readily available, show how you would replace the following
logic gates with 2-input NOR-gates only; (include symbols, logic expressions and equivalent
circuits)
i) A 2-input AND-gate
2
ii) A 2-input OR-gate. (4 Marks )
d) i) Convert the Gray–code 1 1 0 0 1 0 1 1 1 0 1 to its equivalent Binary word. Explain the
steps.
ii) Convert the Binary word 1 1 0 0 1 0 1 1 1 0 1 to its equivalent Gray–code. Explain the
steps. ( 4 Marks)
e) Reduce (simplify) the logic expression using the laws of Boolean algebra and express each as an
SOP.
i) A.B.C + B + B.D + A.B.D + A.C
ii) A.{B + C(A.B + A.C} ( 6 Marks )
f) Determine the Complements (Inverses) and the Dual of each of the following logic functions.
(Do not simplify!)
i) A.B + A + (A.B)
ii) (A + (A + B)).(B + B + C) ( 6 Marks )
QUESTION TWO (20 Marks)
a) A digital logic system has a function represented by the circuit in Fig. Q2.
F
A B C
FIG.Q2
i) Copy the figure and label the output of each of the gates
ii) Derive the raw form of the expression for the output function F.
3
iii) Hence deduce the logic expression of F as a standard Sum-of-Products (SOP) in terms of the
minterms and in terms of the equivalent decimals. (6 Marks )
b) A function X is given by the expression
X = AB + AC + BC
i) Draw the logic circuit diagram of X using basic logic gates only.
ii) Draw the truth–table for the function X
iii) Write down its standard SOP expression in terms of minterms and equivalent decimal
numbers. ( 8 Marks )
c) i) A logic function is given by Y = (A + B).(B + C) . Draw the logic circuit using 2-input NOR –
gates only.
ii) An SOP logic function is expressed as Z = A.B + B.C . Draw the logic circuit of the
function Z using 2–input NAND–gates only. (6 Marks )
QUESTION THREE (20 Marks )
a) A digital logic function F is represented by the K–map of table Q3 (a)
AB
00 01 11 10
00 0 0 0 1
01 1 0 1 1
11 1 0 1 1
10 0 0 0 1
Table Q3 (a)
Copy the table of Q3(a) two times and derive;
i) The simplified Sum–of Products (SOP) expression for the function F
ii) The simplified Product-of–Sums (POS) expression for the function F. (6 Marks )
b) A digital logic system is given by the function
= Sm Y(A, B,C,D) (0,2,3,4,6,7,10,11)
Express the function Y in terms of;
i) its minterms, (ii) its maxterms (8 Marks )
c) Draw the separate K-maps of the function Y in part ( b) and use them to determine the
simplified;
4
i) Sum–of–Products (SOP) form of Y, (ii) Product -of-Sum (POS) form of Y ( 6 Marks )
QUESTION FOUR ( 20 Marks )
a) Represent the decimal number 639, using equivalent binary in;
i) BCD code
ii) Excess-3 code
( 6 Marks )
b) Tabulate a 3-bit Binary code ( in ascending order ) and its equivalent 3-bit Gray code. ( 4 Marks)
c) i) Draw the truth–table for half–adder; where the inputs are A,B and outputs are Sum (S) and
Carry (C )
ii) Write down the SOP expression for S and C
ii) Draw a combined logic circuit diagram for S and C using NAND-gates only.
(8 Marks )
QUESTION FIVE (20 Marks )
a) Diffentiate between Combinational logic and sequential logic. (6 Marks )
b) Derive the table of a 3-bit up counter ( 3 Marks)
c) Hence draw the circuit diagram of a mod-5 asynchronous counter using Toggle flip-flops.
(4 Marks )
d) i ) Define the term multiplexer
ii ) Show how a 4:1 multiplexer may be implemented using NAND-gates only ( 7 Marks )
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